With their reduced footprint, vertical field effect transistors or VFETs are being explored as a device option for scaling beyond the 7 nanometer (nm) technology node. VFETs generally include a fin that forms a vertical channel of the transistor, with source and drain regions situated at a top and bottom of the channel. A gate(s) is/are situated along the sidewalls of the fin channel.
There are, however, notable challenges associated with VFETs fabrication. In particular, forming good junction overlap of the top source and drain terminal to the gate can be difficult due to thinning of the high-κ gate dielectric and hence reliability issues. An alternative is to underlap the junction. However, underlapping the junction significantly increases the external resistance, and thus degrades performance of the transistor.
Accordingly, improved techniques for forming the top source and drain junction of vertical transistors would be desirable.